Field
The present disclosure relates to an electronic device, and more particularly, to a semiconductor device including a plurality of chips and an electronic device including the semiconductor device.
Description of the Related Art
Recent technological advances have continued to increase capacity and speed of semiconductor chips and Integrated Circuits (IC) used in most electronic devices. As large capacity semiconductor chips and ICs have been mounted within small spaces, various attempts for efficiently driving them have been proposed.
In order to enhance an integration level of semiconductor devices, so-called three-dimensional (3D) integration/packaging technology (hereafter, “3D technology”) in which a plurality of semiconductor chips are stacked, has been applied, which improves space utilization efficiency as compared to traditional two-dimensional (2D) methods. A structure that enhances an integration level by reducing a semiconductor chip size using a 3D integration structure of a semiconductor chip is desired.
For realizing such 3D technology, a Through Silicon Via (TSV) method is commonly used. The TSV method improves performance over prior interconnect methods by reducing degradation in terms of data bandwidth and transmission speed deterioration (previously a function of package variation). In the TSV method, by generating a path that penetrates a plurality of semiconductor chips or wafers and by forming an electrode in the path, an electrical connection between semiconductor chips (or layers in a single integrated circuit) is formed. Stacked semiconductor devices that apply a TSV method are directly connected to via without a wire, a package “sub”, or a package ball used in a System-in-Package (SiP) method and a package-on-package (PoP) method. (In the latter packaging methods, a bump or ball is formed between paths that penetrate a plurality of semiconductor chips to electrically connect the chips.)
In a TSV method, because stacked semiconductor chips are directly penetrated, when separate space for penetration is designed, a semiconductor chip design region allocated for active circuits decreases. Moreover, when penetrating the semiconductor chip, the semiconductor chip may be damaged, resulting in increased process cost.